The present invention relates to a method for fabricating a stacked capacitor in a semiconductor configuration in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The one electrode of the stacked capacitor is produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. In addition, the present invention relates to a stacked capacitor fabricated by this method.
The terms p-doped, p+-doped, pxe2x88x92-doped, n-doped, n+-doped, nxe2x88x92-doped are used synonymously with the abbreviations p-type, p+type, p+-type, pxe2x88x92-type, n-type, n+-type, nxe2x88x92-type, as is customary among those skilled in semiconductor technology.
In the case of a method for fabricating a DRAM cell configuration as disclosed in Published, Non-prosecuted German Patent Application DE 195 26 952 A1, a storage capacitor is disposed in a trench and includes an electrode structure with a plurality of elements with a bulbous configuration and whose surface is provided with a storage dielectric and a counter-electrode. The electrode structure is fabricated by employing the etching of pxe2x88x92-doped polysilicon, which etching is selective with respect to p+-doped polysilicon. Therefore, the fact that pxe2x88x92-doped polysilicon can be etched significantly more rapidly (by a factor of the order of magnitude of 100) compared with p+-doped polysilicon is utilized in this case. In the case of the fabrication of a trench-type storage capacitor disclosed in U.S. Pat. No. 5,153,813, dry etching is performed with alternately oppositely doped semiconductor layers, and the fact that the oppositely doped semiconductor layers have different etching rates is utilized in the process. In this way, the surface and hence the capacitance of the capacitor is enlarged.
U.S. Pat. No. 5,637,523 discloses a method in which, in order to enlarge the capacitor area of a stacked capacitor disposed on a semiconductor body, the capacitor is formed from alternately disposed first and second semiconductor layers, which can be etched differently. Examples of these layers are amorphous or polycrystalline silicon having different doping concentrations.
U.S. Pat. No. 5,053,351 describes a method for fabricating a stacked capacitor for a DRAM cell. In the DRAM cell polycrystalline layers and dielectric layers are applied alternately to a semiconductor body and in which the dielectric layers are then removed in a selective etching step, in order in this way to obtain a capacitor area which is as large as possible.
Finally, German Patent DE 195 46 999 C1 discloses a method for fabricating a stacked capacitor on a semiconductor body provided with a transistor, in which, in a manner similar to that in the method disclosed in Published, Non-prosecuted German Patent Application DE 195 26 952 A1, the selective etchability of p+-doped polysilicon and pxe2x88x92-doped polysilicon is utilized in order to produce a lamellar electrode of the stacked capacitor.
On account of the high selective etchability of p+-type polysilicon and pxe2x88x92-type polysilicon, the last-mentioned method has proved to be particularly successful for producing lamella or laminar structures made of p+-type polysilicon, which is used as the first electrode of the stacked capacitor. In the known method, the electrode firstly has applied to it a dielectric (silicon oxide and/or silicon nitride and/or ON or else ONO etc.), after which the counter-electrode is then formed.
The known method, which is extremely expedient for fabricating a stacked capacitor, has a serious disadvantage, however, for the function of a memory cell using the stacked capacitor. The contact-making of the inner electrode of the stacked capacitor, which electrode is inevitably p+-conducting on account of the etching process, with the source/drain terminal region of the transistor provided in the semiconductor body, which terminal region is n+-conducting for other reasons, is not directly possible. This is because the p+n+ junction present in this case forms a diode that severely impairs or even completely prevents the functioning of the DRAM cell. For this reason, a concept has been conceived of heretofore which envisages providing a metallic intermediate layer between the n+-conducting source/drain terminal region of the transistor and the p+-conducting electrode of the stacked capacitor, which ensures a resistive connection between the terminal region and the electrode. Although this makes it possible to provide for entirely satisfactory functioning of the memory cell, the introduction of the metallic intermediate layer, which is buried in the layer structure, has turned out to be problematic, since the rest of the process for fabricating the stacked capacitor is thereby altered and requires process variants which have not been able to be resolved heretofore. Even though, therefore, the utilization of the etching selectivity between p+-type polysilicon and pxe2x88x92-type polysilicon is desirable in the fabrication of a stacked capacitor, it has not been possible to date to solve the problems arising with the p30 n30  junction between the internal p+-type electrode of the stacked capacitor and the n+-type source/drain terminal region, which p30 n30  junction inevitably occurs in the case of n-channel transistors. Therefore, it has not been possible to date to successfully fabricate stacked capacitors in the context of n-channel transistors by utilizing the selective etchability of p+-type polysilicon and pxe2x88x92-type polysilicon.
It is accordingly an object of the invention to provide a method for fabricating a stacked capacitor in a semiconductor configuration, and a stacked capacitor fabricated by the method that overcome the above-mentioned disadvantages of the prior art methods and devices of this general type, which utilizes the selective etchability of p+-type polysilicon and pxe2x88x92-type polysilicon and can readily be used with n-channel transistors; in addition, the intention is to provide a stacked capacitor fabricated by the method.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a capacitor in a semiconductor configuration, which includes: providing a transistor with a source/drain region formed in a semiconductor body and a terminal region of a first conductivity type connected to the source/drain region; applying alternating semiconductor layers of different doping concentrations of a second conductivity type including weaker doped layers and stronger doped layers on the terminal region resulting in the alternating semiconductor layers having different etching rates for forming one electrode of a stacked capacitor connected to the terminal region; etching the alternating semiconductor layers resulting in selective removal of some of the alternatively semiconductor layers for forming the one electrode of the stacked capacitor from remaining layers of the alternating semiconductor layers; and performing a doping reversal of the remaining layers remaining after the etching step to the first conductivity type for forming the one electrode of the stacked capacitor.
In the case of the method of the type mentioned in the introduction, the object is achieved according to the invention by virtue of the fact that after the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed.
The invention thus follows a path that departs completely from the previous prior art. Instead of adopting special metalizations or measures for ruling out the disadvantages associated with the p30 n30  junction which is inevitably present between the p+-type electrode and the n+-type terminal region, in the case of the invention the p30 n30  junction itself is eliminated. For this purpose, after the etching away of the pxe2x88x92-type layer, if appropriate after being covered with a silicon dioxide layer, in a preferred manner the p+-type electrode of the capacitor is first of all subjected to a heat treatment in a vacuum or in a suitable gas atmosphere of nitrogen, during which the p+-type doping is depleted to a great extent across the surface. Specifically, since the thickness of the lamellae of the p+-type electrode is in the region of less than 30 nm, considerable depletion of the p+-type dopant, that is to say boron, occurs during customary heat treatments in the temperature interval between about 750xc2x0 C. and 1150xc2x0 C.
Subsequently, the electrode with the depleted p-doping then has its doping reversed by the introduction of, for example, arsenic or phosphorus up to the saturation limit of the semiconductor material, that is to say silicon, or to a point beyond the limit. Ion implantation may preferably be employed for the introduction of the doping-reversal dopant, that is to say arsenic or phosphorus in the present example. However, coating or in-diffusion is also possible.
Following an after treatment of the electrode, for example an annealing step in the case of ion implantation or the removal of the coating, the electrode is provided with an n+-type doping and, consequently, can be connected without difficulty to the terminal region of the transistor or another n-conducting region.
In the explanations above it is assumed that the etching selectivity between the p+-type polysilicon and the pxe2x88x92-type polysilicon is utilized, so that the first conductivity type is n-type conductivity and the second conductivity type is p-type conductivity. However, the present invention can also advantageously be applied when the different etching rates of n-conducting semiconductor layers doped to different extents are used for forming a lamella electrode of a stacked capacitor, in order to enable an n-conducting electrode which is then present to be connected to a p+-type terminal region.
In the preferred exemplary embodiment of the invention, in which a boron-doped electrode has its doping reversed, the fact that boron has distinctly less solid solubility in silicon than arsenic or phosphorus, for example, is advantageously utilized. It is thus possible to perform the doping reversal. An additional fact that is utilized in this case is the fact that the lamellae of the p+-type electrode are so thin that during the aforementioned heat treatment in a vacuum or in a suitable gas atmosphere, even if the lamellae are covered with silicon dioxide or layers containing silicon dioxide, a significant part of the boron diffuses into the vacuum surrounding the electrode, the atmosphere or the silicon-dioxide covering layer and can thus actually be removed even before the doping reversal, for example by ion implantation of arsenic or phosphorus.
A stacked capacitor fabricated by the method according to the invention is distinguished by the fact that residues of a dopant of the second conductivity type are present in at least one of its electrodes made of polycrystalline silicon which is heavily doped with dopant of the first conductivity type.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for fabricating a stacked capacitor in a semiconductor configuration, and a stacked capacitor fabricated by this method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.